A computer uses a processor to perform data processing according to instructions. A pipeline processor is known as a kind of processor.
A pipeline processor improves efficiency of executing instructions by performing parallel processing in stages having a series relationship. The stages are separated from each other by pipeline registers. Operation results produced by the instructions are written into a general purpose register.
One of the factors that cause performance deterioration of a pipeline processor is data hazard. The data hazard occurs when data dependency exists in a series of instructions to be executed consecutively. When two instructions have such a relationship that a subsequent instruction has to use an operation result of a preceding instruction, a short interval between the instructions leads to a state in which execution of the subsequent instruction is stopped until the operation result of the preceding instruction is written to the general purpose register.
An approach to reduce influence of such data hazard is bypassing. The bypassing is a technique to utilize data being processed in a pipeline, without waiting the data to be written into the general purpose register. Thus, the subsequent instruction can use data before the operation result produced by the preceding instruction is written into the general purpose register. The use of bypassing enables arithmetic processing to be performed continuously without stopping the pipeline.
A bypass circuit is provided to enable the bypassing. The bypass circuit is a circuit to transfer data produced in a mid-stage in a pipeline to a stage in a pipeline to execute a subsequent instruction. The latter stage is a stage, for example, to read data from the general purpose register.
As a processor becomes faster and more sophisticated, power consumption of the processor tends to increase. Thus, reduction in power consumption of the processor has been desired.
A technique to reduce power consumption of a pipeline processor having a bypass circuit is described on page 4 and FIG. 1 in Japanese Patent Application Publication No. 9-91140.
The publication discloses that a validity testing logic is provided in an instruction decoder to decode and output instructions.
The validity testing logic is designed to determine the validity of an instruction to a register according to an inputted instruction. If a determination result of the validity testing logic does not show the validity, data is not read from the general purpose register.
One of the cases that the validity testing logic does not show the validity is the case that the instruction does not use the general purpose register. Another of the cases is the case that bypassed data is used by operation of the bypass circuit. When the bypass circuit operates, data is not read from the general purpose register. As a result, power consumption is reduced by the amount to be used for the reading.
Even in the pipeline processor disclosed in the publication, the bypass circuit can function effectively only when there is an extremely short execution interval between preceding and subsequent instructions that have data dependency. In a case where any other instructions are issued between the preceding and the subsequent instructions, the operation result of the preceding instruction is written into the general purpose register by the time when the subsequent instruction is executed.
Thus, data does not remain in the pipeline in which the preceding instruction is processed. Consequently, execution of the subsequent instruction requires the operation result produced by the preceding instruction and to be read from the general purpose register to which the operation result has been written.
When there is a long execution interval between the instructions having data dependency, stored data is read from the general purpose register to cause power consumption for the reading.
When a subsequent instruction is an instruction to overwrite the general purpose register on which a write has been performed by a preceding instruction, an unnecessary writing is performed into the general purpose register by the preceding instruction, and power consumption occurs for the writing.